Chaitanya is a pre-final year B.Tech student in Electronics and Communication Engineering at IIT (BHU) Varanasi, with a strong interest in embedded systems, digital design, and software-hardware co-design.

He is currently contributing to OpenROAD through Google Summer of Code 2025, implementing support for Rectilinear Floorplans in OpenROAD by extending user interfaces, language bindings, and backend C++ modules. As a Linux Foundation mentee with RISC-V International, he developed a hardware abstraction layer for posit arithmetic, enhanced the SoftPosit-cpp library, and integrated it with CI/CD pipelines and Python tooling.

His embedded systems work includes designing secure bootloaders with AES decryption, digital signature verification, and Root of Trust, optimized for memory-constrained environments. His FPGA and digital design experience spans building NAND flash controllers in Verilog and Embedded C and implementing RISC-V CPUs.

Previously, he contributed to Apertium under GSoC 2024 and has co-authored papers on neuromorphic computing and NAND flash reliability. Chaitanya enjoys tackling engineering problems at the intersection of algorithms, architecture, and system design.