OpenRAM is an award winning open-source Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies. Most recently, it has created memories that are included on all of the eFabless/Google/Skywater MPW tape-outs.

Layout verses Schematic (LVS) visualization

Create a visualization interface to debug layout verses schematic mismatches in Magic layout editor. Results will be parsed from a JSON output of Netgen.

Jesse Cirimelli-Low
Jesse Cirimelli-Low
Ph.D. Student, UC Santa Cruz

Jesse Cirimelli-Low is a PhD student at University of California, Santa Cruz